The present invention generally relates to semiconductor processing, and more particularly relates to a system and a method for modifying the mask layout data used to generate photomasks.
The manufacturing of semiconductor devices is dependent upon the accurate replication of device design data onto the surface of a semiconductor substrate. The minimum feature sizes of integrated circuits are continuously decreasing in order to increase the packing density of the various semiconductor devices formed thereby. With this size reduction, however, various steps within the integrated circuit fabrication process become more difficult. Photolithography, the manufacture of photomasks (reticles), and optical proximity correction (OPC) are areas that experience unique challenges as feature sizes shrink.
Photolithography involves selectively exposing regions of a resist-coated silicon wafer to form a radiation pattern. Once exposure is complete, the exposed resist is developed in order to selectively expose and protect the various regions on the silicon wafer defined by the exposure pattern (e.g, silicon regions in the substrate, polysilicon on the substrate, or insulating layers such as silicon dioxide).
An integral component of a photolithography system is a reticle (often called a mask or photomask) which includes a pattern thereon corresponding to features to be formed in a layer on the substrate. A reticle typically includes a transparent glass plate covered with a patterned light blocking material such as chrome. The reticle is placed between a radiation source producing radiation of a pre-selected wavelength (e.g., ultraviolet light) and a focusing lens which may form part of a stepper apparatus. Placed beneath the stepper is a resist-covered silicon wafer. When the radiation from the radiation source is directed onto the reticle, light passes through the glass (in the regions not containing the chrome patterns) and projects onto the resist-covered silicon wafer. In this manner, an image of the reticle is transferred to the resist.
The mask layout data, or mask layout, is a digital representation of a desired integrated circuit pattern. This digital representation is used by the reticle manufacturer to generate the reticle. Typically, the mask layout data is generated using computer aided design (CAD) techniques. The pattern features correspond to the features of the integrated circuit devices that are to be fabricated. The quality of the mask patterns on the mask are critical to generating the desired integrated circuit features on the wafer. Critical dimensions include the size of patterns across the mask, such as line width and spacing.
A mask is a optically clear quartz substrate with a chrome pattern. To generate a mask, a layer of photoresist is applied to a chrome coated reticle blank.
The resist (sometimes referred to as the xe2x80x9cphotoresistxe2x80x9d) is provided as a thin layer of radiation-sensitive material. The mask layout design is transferred to the reticle using a mask writer, or mask writer system, for instance, a laser writer or an electron beam (e-beam) writer. A laser writer transfers the mask layout data to the reticle by selectively exposing areas of the photoresist to ultra-violet (UV) light. An e-beam pattern transfers the mask layout data to the reticle by selectively exposing areas of the photoresist to an electron beam. After pattern generation, the exposed photoresist is removed with a chemical solution, and the exposed areas of chrome are etched away leaving a quartz surface. The remaining photoresist is then removed, and the finished mask has the mask layout data pattern on its surface.
To transfer the reticle pattern to a semiconductor substrate, a thin-layer of resist is spin-coated over the entire silicon wafer surface. The resist material is classified as either positive or negative depending on how it responds to the light radiation. Positive resist, when exposed to radiation becomes more soluble and is thus more easily removed in a development process. As a result, a developed positive resist contains a resist pattern corresponding to the dark regions on the reticle. Negative resist, in contrast, becomes less soluble when exposed to radiation. Consequently, a developed negative resist contains a pattern corresponding to the transparent regions of the reticle.
As UV light passes through the reticle to develop the resist, it is diffracted and scattered by the edges of the chrome. This causes the projected image to exhibit some rounding and other optical distortion. While such effects pose relatively little difficulty in layouts with large features (e.g., features with critical dimensions greater than one micron), they can not be ignored in present day layouts where critical dimensions are about 0.25 micron or smaller. The problem highlighted above becomes more pronounced in integrated circuit designs having feature sizes below the wavelength of the radiation used in the photolithographic process.
To remedy this problem, a reticle correction technique known as optical proximity correction (OPC) has been developed. OPC involves the adding of dark regions to and/or the subtracting of dark regions from portions of a reticle to overcome the distorting effects of diffraction and scattering when transferring the mask patterns to the substrate. Typically, OPC is performed on the mask layout data. First, the mask layout data is evaluated with software to identify regions where optical distortion will result. Then the OPC features are added to the mask layout data to compensate for the distortion. The mask layout data with the OPC features added is referred to as the optical proximity corrected mask layout data, or optical proximity corrected mask layout. The resulting pattern of the optical proximity corrected mask layout is ultimately transferred to the reticle glass. Some optical proximity correction takes the form of xe2x80x9cserifs.xe2x80x9d Serifs are small, appendage-type addition or subtraction regions typically made at corner regions on reticle designs. As used in the present invention, the term serif is used to identify both addition and subtraction regions.
FIG. 1 shows a mask design layout feature 10. Unfortunately, as shown in FIG. 2, the mask feature 20 as written by the mask writer can deviate from the layout feature 10, for instance, right angles will exhibit rounding. Right angles are desirable features of semiconductor devices, and OPC correction features, such as serifs. For instance, the intersection of a transistor and a gate line often forms a T-shaped feature, and a serif often is square in shape. The shape of the device features and the OPC, such as serifs, must be accurately reproduced onto the mask to accurately pattern the semiconductor substrate. Rounding of these features interferes with optical proximity correction, negatively impacts device performance, and adds a level of nonuniformity between transistors which is undesirable. For instance, a rounded serif will not yield optimal optical proximity correction. Similarly, a mask with rounding of the T-shaped device features will not produce right angles on the semiconductor, and this will impact the transistor performance and the device packing density.
Since rounding is highly undesirable and results in degraded transistor performance, increased transistor layout spacing (which decreases device packing density), and interference with optical proximity correction, there is an unmet need for a system and method to reduce comer rounding. This need is especially felt in OPC, where the OPC features necessary to correct for optical distortion are often of small dimension with sharp angles and other difficult to write features. A system and method for improving the writeability of OPC features onto the reticle is needed.
The present invention generally relates to a system and a method for improving the manufacture of masks used in manufacturing integrated circuits. Mask features and portions of mask features can be very small, such as an optical proximity correction (OPC) feature, including serifs. Since small features are difficult to write onto the mask accurately, the mask layout data may not be reproduced on the mask with fidelity. In the present invention, a mask is produced from a mask design layout. The difference between the layout features and the mask features as written is termed the area loss. The area loss is determined by using edge detection techniques, such as by inspection with a scanning electron microscope. The area loss information is fed into a computer system, which generates sizing corrections to adjust the mask writer.
In one aspect of the invention, the mask design layout data is modified by the sizing corrections, and a corrected mask is produced using the corrected mask design layout data. The resulting features on the corrected mask more accurately represent the design layout features. In another aspect of the invention, a database of sizing corrections for various feature types and sizes can be generated and stored. A mask design layout is modified by the sizing corrections, and when the mask is written, the resulting mask exhibits greater fidelity.
Another aspect of the present invention relates to a method of improving the manufacture of a mask. The method includes providing a mask layout, and writing a mask from the mask layout. The mask layout includes a mask layout feature, and the mask includes a mask feature corresponding to the mask layout feature. Then one or more area loss data comprise substantially a difference between a portion of the mask feature and a corresponding portion of the mask layout feature are determined. The mask layout is modified in response to the determined one or more area loss data. A corrected mask may be written from the modified mask layout.
The one or more area loss data may be determined by an edge detection technique. The edge detection technique may include detecting one or more edge features of the portion of the mask feature with a scanning electron microscope. The method may further include generating one or more edge data from the one or more edge features, such as one or more radii of the portion of the mask feature. The one or more edge data may be input into a processor, and the processor may calculate the one or more area loss data by comparing the one or more edge data to the corresponding portion of the mask layout feature. The portion of the mask layout feature may be an optical proximity correction feature. The mask layout may be modified by determining one or more sizing correction data from the area loss data, and a database of one or more sizing correction data may be generated. The one or more sizing correction data may be determined by inputting the one or more area loss data into a processor that calculates the one or more sizing correction data. The present invention may be used to modify any type of mask layout, such as an optical proximity corrected mask layout. The mask layout may include a plurality of mask layout features and the mask may include a plurality of mask features corresponding to the plurality of mask layout features.
Yet another aspect of the present invention relates to a method of improving the manufacture of a mask. The method includes providing a mask layout, and writing a mask from the mask layout. The mask layout includes a mask layout feature, and the mask includes a mask feature corresponding to the mask layout feature. An area loss is determined, which comprises substantially a difference between a portion of the mask feature and a corresponding portion of the mask layout feature. Then one or more sizing corrections are generated from the area loss, and the one or more sizing corrections are stored in a database. The mask layout may be modified in accordance with the one or more sizing corrections stored in the database, and a corrected mask may be written from the modified mask layout.
The area loss may be determined by an edge detection technique. The edge detection technique may include detecting one or more edges of the portion of the mask feature with a scanning electron microscope. The method may further include determining one or more edge data by the edge detection technique, such as one or more radii of the portion of the mask feature. The one or more edge data may be input into a processor that calculates the area loss. The portion of the mask feature may be an optical proximity correction feature. The one or more sizing corrections may be determined by inputting the area loss into a processor that calculates the one or more sizing correction data. The present invention may be used to modify any type of mask layout, such as an optical proximity corrected mask layout. The mask layout may include a plurality of mask layout features and the mask may include a plurality of mask features corresponding to the plurality of mask layout features.
Another aspect of the present invention relates to a system for manufacturing a mask. The system includes an edge detector, a processor, and a mask writer operatively coupled to the processor. The edge detector determines one or more edge data of a portion of a mask feature. The processor receives the one or more edge data and is operatively coupled to an algorithm that calculates one or more area loss data from the one or more edge data. The mask writer receives the one or more area loss data. The mask writer may include an algorithm for determining one or more sizing correction data from the one or more area loss data. The system may further include a database operatively coupled to the mask writer to store the one or more sizing correction data. The edge detector may be a scanning electron microscope. The mask writer can include an algorithm for modifying a mask layout in accordance with the one or more sizing correction data. The system may be used to calculate area loss data on any portion of the mask feature, such as an optical proximity correction feature. The system may be used to modify any type of mask layout, such as an optical proximity corrected mask layout. The mask layout may include a plurality of mask layout features and the mask may include a plurality of mask features corresponding to the plurality of mask layout features.
Still yet another aspect of the present invention relates to a system for manufacturing a mask. The system includes an edge detector, a processor, and a mask writer operatively coupled to the processor. The edge detector determines one or more edge data. The processor receives the one or more edge data and is operatively coupled to one or more algorithms that determine one or more sizing correction data from the one or more edge data. The mask writer receives the one or more sizing correction data. The mask writer may further include at least one algorithm for modifying a mask layout in accordance with the one or more sizing correction data.
The system can further include a database operatively coupled to the mask writer to store the one or more sizing correction data. The edge detector may be a scanning electron microscope. The system may be used to modify any type of mask layout, such as an optical proximity corrected mask layout. The mask layout may include a plurality of mask layout features and the mask may include a plurality of mask features corresponding to the plurality of mask layout features. The mask layout may include one or more optical proximity correction features.
Another aspect of the present invention relates to a system for manufacturing a mask. The system includes a database, a processor, and a mask writer operatively coupled to the processor. The database includes one or more sizing correction data that are associated with the difference between a portion of a mask layout feature and a corresponding portion of a mask feature. The portion of the mask layout feature may be an optical proximity correction feature. The processor receives the one or more sizing correction data and modifies a mask layout in accordance with the one or more sizing correction data. The mask writer receives the modified mask layout and generates a mask in accordance with the modified mask layout. The processor and the mask writer may be components of a mask writer system. The system may be used to modify any type of mask layout, such as an optical proximity corrected mask layout.
Another aspect of the present invention relates to a data storage medium. The data storage medium includes one or more sizing correction data. The sizing correction data correspond to one or more area loss data, and the area loss data comprise substantially a difference between a mask layout feature and a mask feature. The area loss data may be determined by an edge detection technique, and the sizing corrections may be determined by inputting the area loss data to a processor operatively coupled to an algorithm for calculating the sizing correction data. The edge detection technique may include detecting one or more edges of the mask feature with a scanning electron microscope. The edge detection technique may further include generating one or more edge data, such as one or more radii of the mask feature. The area loss data may be determined by inputting the edge data into a processor that is operatively coupled to an algorithm for calculating the area loss data. The second mask layout may be modified in accordance with the sizing correction data stored in the data storage medium. A corrected mask may be written from the modified second mask layout. The data storage medium may contain sizing correction data corresponding to any portion of a mask feature, such as an optical proximity correction feature. The data storage medium may be used to modify any type of mask layout data, such as an optical proximity corrected mask layout.